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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\impl\gwsynthesis\USB_AUDIO.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\USB_AUDIO.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Nov 12 13:55:33 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>47584</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>27704</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>76</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>598</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk27mhz</td>
<td>Base</td>
<td>37.037</td>
<td>27.000
<td>0.000</td>
<td>18.519</td>
<td></td>
<td></td>
<td>clk27mhz_ibuf/I </td>
</tr>
<tr>
<td>n43_13</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F </td>
</tr>
<tr>
<td>sk9822_dir/clk_delay[4]</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay_4_s0/Q </td>
</tr>
<tr>
<td>HP_BCK_d</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>u_usb_audio/clk_1p536m_s1/Q </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.000
<td>0.000</td>
<td>8.333</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.000
<td>0.000</td>
<td>8.333</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>33.333</td>
<td>30.000
<td>0.000</td>
<td>16.667</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUTD3 </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk27mhz</td>
<td>27.000(MHz)</td>
<td>69.894(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>n43_13</td>
<td>100.000(MHz)</td>
<td>246.975(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>100.000(MHz)</td>
<td>268.559(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>HP_BCK_d</td>
<td>100.000(MHz)</td>
<td>285.632(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>60.000(MHz)</td>
<td>90.209(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk27mhz</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk27mhz</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>n43_13</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>n43_13</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sk9822_dir/clk_delay[4]</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sk9822_dir/clk_delay[4]</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>HP_BCK_d</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>HP_BCK_d</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_8_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_9_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_11_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_12_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_13_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_14_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_15_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_16_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_17_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_18_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_19_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_20_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_21_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right3_d2_22_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>18</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>19</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>20</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>21</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_14_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>22</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_15_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>23</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_16_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>24</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_17_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>25</td>
<td>-4.313</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
<td>mic_serial_inst/mic_data_right2_d2_18_s0/CE</td>
<td>n43_13:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.370</td>
<td>0.059</td>
<td>4.554</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.074</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[4]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.323</td>
</tr>
<tr>
<td>2</td>
<td>0.074</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[3]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.323</td>
</tr>
<tr>
<td>3</td>
<td>0.076</td>
<td>mic_serial_inst/mic_data_left3_d2_20_s0/Q</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[14]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.325</td>
</tr>
<tr>
<td>4</td>
<td>0.190</td>
<td>xcorr3/mic_data_store_inst2/start_flag_s1/Q</td>
<td>xcorr3/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.202</td>
</tr>
<tr>
<td>5</td>
<td>0.190</td>
<td>xcorr3/mic_data_store_inst1/start_flag_s1/Q</td>
<td>xcorr3/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.202</td>
</tr>
<tr>
<td>6</td>
<td>0.190</td>
<td>xcorr2/mic_data_store_inst2/start_flag_s1/Q</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.202</td>
</tr>
<tr>
<td>7</td>
<td>0.190</td>
<td>xcorr2/mic_data_store_inst1/start_flag_s1/Q</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.202</td>
</tr>
<tr>
<td>8</td>
<td>0.190</td>
<td>xcorr1/mic_data_store_inst2/start_flag_s1/Q</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.202</td>
</tr>
<tr>
<td>9</td>
<td>0.190</td>
<td>xcorr1/mic_data_store_inst1/start_flag_s1/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.202</td>
</tr>
<tr>
<td>10</td>
<td>0.198</td>
<td>mic_serial_inst/mic_data_left2_d2_20_s0/Q</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[14]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.447</td>
</tr>
<tr>
<td>11</td>
<td>0.201</td>
<td>mic_serial_inst/mic_data_right1_d2_8_s0/Q</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[2]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.450</td>
</tr>
<tr>
<td>12</td>
<td>0.202</td>
<td>mic_serial_inst/mic_data_left3_d2_12_s0/Q</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[6]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.451</td>
</tr>
<tr>
<td>13</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_left2_d2_18_s0/Q</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[12]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>14</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_left2_d2_16_s0/Q</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[10]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>15</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_left2_d2_10_s0/Q</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[4]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>16</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_left2_d2_8_s0/Q</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[2]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>17</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_left3_d2_21_s0/Q</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[15]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>18</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_left3_d2_13_s0/Q</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[7]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>19</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[6]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>20</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[5]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>21</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[2]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>22</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[1]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>23</td>
<td>0.213</td>
<td>mic_serial_inst/mic_data_right2_d2_6_s0/Q</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[0]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>24</td>
<td>0.216</td>
<td>mic_serial_inst/mic_data_right1_d2_17_s0/Q</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[11]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.465</td>
</tr>
<tr>
<td>25</td>
<td>0.216</td>
<td>mic_serial_inst/mic_data_right1_d2_16_s0/Q</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[10]</td>
<td>clk27mhz:[R]</td>
<td>clk27mhz:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.465</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>2</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>3</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>4</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>5</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>6</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>7</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>8</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>9</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>10</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>11</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>12</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>13</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>14</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>15</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>16</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>17</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>18</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>19</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>20</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>21</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>22</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>23</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>24</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
<tr>
<td>25</td>
<td>13.936</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>2.696</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>2</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>3</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>4</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>5</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>6</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>7</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>8</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>9</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>10</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>11</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>12</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>13</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>14</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>15</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>16</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>17</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>18</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>19</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>20</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>21</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>22</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>23</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>24</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
<tr>
<td>25</td>
<td>1.860</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.871</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction_2_s0</td>
</tr>
<tr>
<td>2</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction_1_s0</td>
</tr>
<tr>
<td>3</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction_0_s0</td>
</tr>
<tr>
<td>4</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction2_3_s0</td>
</tr>
<tr>
<td>5</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction2_2_s0</td>
</tr>
<tr>
<td>6</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction3_3_s0</td>
</tr>
<tr>
<td>7</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction3_2_s0</td>
</tr>
<tr>
<td>8</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/direction3_1_s0</td>
</tr>
<tr>
<td>9</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/sk9822_ck_s0</td>
</tr>
<tr>
<td>10</td>
<td>3.285</td>
<td>4.285</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sk9822_dir/clk_delay[4]</td>
<td>sk9822_dir/send_bit_cnt_1_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C45[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_8_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C45[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_8_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_8_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C45[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C45[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_9_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C45[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_9_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_9_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C45[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C49[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_11_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C49[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_11_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_11_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R49C49[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C49[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_12_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C49[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_12_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_12_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R49C49[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C49[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_13_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C49[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_13_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_13_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C49[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C49[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_14_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C49[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_14_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_14_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C49[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C48[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_15_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C48[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_15_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_15_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C48[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C48[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_16_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C48[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_16_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_16_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C48[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C46[0][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_17_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C46[0][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_17_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_17_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C46[0][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C46[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_18_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C46[2][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_18_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_18_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C46[2][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C49[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_19_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C49[1][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_19_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_19_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R47C49[1][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C43[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_20_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C43[2][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_20_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_20_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R47C43[2][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C50[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_21_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C50[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_21_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_21_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C50[0][A]</td>
<td>mic_serial_inst/mic_data_right3_d2_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right3_d2_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C50[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right3_d2_22_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C50[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_22_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right3_d2_22_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C50[1][B]</td>
<td>mic_serial_inst/mic_data_right3_d2_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C48[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_7_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C48[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C48[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C48[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_8_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C48[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C48[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_9_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C47[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C47[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C47[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_10_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C47[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C47[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C46[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_11_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C46[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C46[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C46[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_12_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C46[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R45C46[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C44[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_14_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C44[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_14_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_14_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C44[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C44[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_15_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C44[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_15_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_15_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C44[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C43[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_16_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C43[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_16_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_16_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C43[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C43[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_17_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C43[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_17_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_17_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C43[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.313</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>375.539</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.226</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>mic_serial_inst/mic_data_right2_d2_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n43_13:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>370.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n43_13</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>235</td>
<td>R38C40[1][B]</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F</td>
</tr>
<tr>
<td>370.985</td>
<td>0.985</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R40C47[0][A]</td>
<td>mic_serial_inst/microphoneIns/finished_left_s1/CLK</td>
</tr>
<tr>
<td>371.217</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>196</td>
<td>R40C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/microphoneIns/finished_left_s1/Q</td>
</tr>
<tr>
<td>373.357</td>
<td>2.140</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R39C45[2][A]</td>
<td>mic_serial_inst/n1869_s1/I0</td>
</tr>
<tr>
<td>373.927</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>162</td>
<td>R39C45[2][A]</td>
<td style=" background: #97FFFF;">mic_serial_inst/n1869_s1/F</td>
</tr>
<tr>
<td>375.539</td>
<td>1.612</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C42[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_18_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>370.370</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>371.053</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>371.296</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C42[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_18_s0/CLK</td>
</tr>
<tr>
<td>371.261</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>mic_serial_inst/mic_data_right2_d2_18_s0</td>
</tr>
<tr>
<td>371.226</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C42[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.059</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.985, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.570, 12.516%; route: 3.752, 82.390%; tC2Q: 0.232, 5.094%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.074</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.183</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C47[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_10_s0/CLK</td>
</tr>
<tr>
<td>1.061</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R45C47[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_10_s0/Q</td>
</tr>
<tr>
<td>1.183</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.074</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.183</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C47[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_9_s0/CLK</td>
</tr>
<tr>
<td>1.061</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R45C47[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_9_s0/Q</td>
</tr>
<tr>
<td>1.183</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.076</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.185</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left3_d2_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C45[0][B]</td>
<td>mic_serial_inst/mic_data_left3_d2_20_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C45[0][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left3_d2_20_s0/Q</td>
</tr>
<tr>
<td>1.185</td>
<td>0.123</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[14]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr3/mic_data_store_inst2/start_flag_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C50[0][A]</td>
<td>xcorr3/mic_data_store_inst2/start_flag_s1/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R44C50[0][A]</td>
<td style=" font-weight:bold;">xcorr3/mic_data_store_inst2/start_flag_s1/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[10]</td>
<td style=" font-weight:bold;">xcorr3/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[10]</td>
<td>xcorr3/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>0.872</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[10]</td>
<td>xcorr3/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr3/mic_data_store_inst1/start_flag_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr3/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C51[2][A]</td>
<td>xcorr3/mic_data_store_inst1/start_flag_s1/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>14</td>
<td>R48C51[2][A]</td>
<td style=" font-weight:bold;">xcorr3/mic_data_store_inst1/start_flag_s1/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[11]</td>
<td style=" font-weight:bold;">xcorr3/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[11]</td>
<td>xcorr3/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>0.872</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[11]</td>
<td>xcorr3/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr2/mic_data_store_inst2/start_flag_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C52[0][B]</td>
<td>xcorr2/mic_data_store_inst2/start_flag_s1/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R43C52[0][B]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/start_flag_s1/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>0.872</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr2/mic_data_store_inst1/start_flag_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C50[1][A]</td>
<td>xcorr2/mic_data_store_inst1/start_flag_s1/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>14</td>
<td>R43C50[1][A]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst1/start_flag_s1/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>0.872</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/mic_data_store_inst2/start_flag_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R51C47[2][A]</td>
<td>xcorr1/mic_data_store_inst2/start_flag_s1/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R51C47[2][A]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst2/start_flag_s1/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>0.872</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>xcorr1/mic_data_store_inst1/start_flag_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R50C47[2][A]</td>
<td>xcorr1/mic_data_store_inst1/start_flag_s1/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>14</td>
<td>R50C47[2][A]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/start_flag_s1/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>0.872</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.198</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left2_d2_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C49[1][B]</td>
<td>mic_serial_inst/mic_data_left2_d2_20_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C49[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left2_d2_20_s0/Q</td>
</tr>
<tr>
<td>1.307</td>
<td>0.245</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[14]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.201</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.309</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right1_d2_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C43[1][A]</td>
<td>mic_serial_inst/mic_data_right1_d2_8_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R47C43[1][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right1_d2_8_s0/Q</td>
</tr>
<tr>
<td>1.309</td>
<td>0.248</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.248, 55.078%; tC2Q: 0.202, 44.922%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.202</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.311</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left3_d2_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C44[1][B]</td>
<td>mic_serial_inst/mic_data_left3_d2_12_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C44[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left3_d2_12_s0/Q</td>
</tr>
<tr>
<td>1.311</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left2_d2_18_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C49[2][A]</td>
<td>mic_serial_inst/mic_data_left2_d2_18_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R45C49[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left2_d2_18_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left2_d2_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C49[0][A]</td>
<td>mic_serial_inst/mic_data_left2_d2_16_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R45C49[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left2_d2_16_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left2_d2_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C49[0][A]</td>
<td>mic_serial_inst/mic_data_left2_d2_10_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C49[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left2_d2_10_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left2_d2_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C49[2][B]</td>
<td>mic_serial_inst/mic_data_left2_d2_8_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C49[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left2_d2_8_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[15]</td>
<td>xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left3_d2_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C44[2][A]</td>
<td>mic_serial_inst/mic_data_left3_d2_21_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C44[2][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left3_d2_21_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[15]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_left3_d2_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C44[1][B]</td>
<td>mic_serial_inst/mic_data_left3_d2_13_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R43C44[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_left3_d2_13_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[7]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[13]</td>
<td>xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C46[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_12_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R45C46[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_12_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C46[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_11_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R45C46[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_11_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C48[1][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_8_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R45C48[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_8_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C48[0][A]</td>
<td>mic_serial_inst/mic_data_right2_d2_7_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R45C48[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_7_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.322</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right2_d2_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C46[2][B]</td>
<td>mic_serial_inst/mic_data_right2_d2_6_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R47C46[2][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right2_d2_6_s0/Q</td>
</tr>
<tr>
<td>1.322</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td style=" font-weight:bold;">xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[14]</td>
<td>xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.216</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.325</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right1_d2_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C41[1][B]</td>
<td>mic_serial_inst/mic_data_right1_d2_17_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R45C41[1][B]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right1_d2_17_s0/Q</td>
</tr>
<tr>
<td>1.325</td>
<td>0.263</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.263, 56.544%; tC2Q: 0.202, 43.456%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.216</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.325</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.109</td>
</tr>
<tr>
<td class="label">From</td>
<td>mic_serial_inst/mic_data_right1_d2_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk27mhz:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R45C41[0][A]</td>
<td>mic_serial_inst/mic_data_right1_d2_16_s0/CLK</td>
</tr>
<tr>
<td>1.062</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R45C41[0][A]</td>
<td style=" font-weight:bold;">mic_serial_inst/mic_data_right1_d2_16_s0/Q</td>
</tr>
<tr>
<td>1.325</td>
<td>0.263</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td style=" font-weight:bold;">xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/DI[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk27mhz</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>827</td>
<td>IOT27[A]</td>
<td>clk27mhz_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0/CLKA</td>
</tr>
<tr>
<td>1.109</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R46[12]</td>
<td>xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/sdpx9b_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.263, 56.544%; tC2Q: 0.202, 43.456%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C53[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C53[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C52[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C52[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C53[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C52[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C53[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C53[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C52[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C52[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C52[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C52[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C50[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C50[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C53[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C53[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C53[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C53[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C51[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C51[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C51[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C53[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C49[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C49[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C48[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C48[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C48[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C48[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C50[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C50[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C47[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C47[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C47[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C49[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C49[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C44[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C44[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R3C44[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C52[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C52[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C52[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C52[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>13.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.969</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.337</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.569</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.722</td>
<td>0.153</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>2.239</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>4.033</td>
<td>1.794</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C51[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.760</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.004</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C51[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLK</td>
</tr>
<tr>
<td>17.969</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C51[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 19.178%; route: 1.947, 72.216%; tC2Q: 0.232, 8.606%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C53[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C52[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C53[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C53[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C52[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C52[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C52[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C52[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C50[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C53[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C53[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C53[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C51[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C51[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C51[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C53[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C49[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C48[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C48[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C48[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C50[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C50[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C47[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C47[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C47[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C49[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C49[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C44[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C44[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C44[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C52[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C52[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C52[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C52[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C52[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.860</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.479</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R5C43[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C43[2][B]</td>
<td>led_d_s0/I0</td>
</tr>
<tr>
<td>1.980</td>
<td>0.384</td>
<td>tINS</td>
<td>FR</td>
<td>407</td>
<td>R5C43[2][B]</td>
<td style=" background: #97FFFF;">led_d_s0/F</td>
</tr>
<tr>
<td>3.149</td>
<td>1.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C51[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.094</td>
<td>1.094</td>
<td>tCL</td>
<td>RR</td>
<td>8274</td>
<td>PLL_L[0]</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.278</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C51[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLK</td>
</tr>
<tr>
<td>1.289</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C51[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.384, 20.519%; route: 1.286, 68.740%; tC2Q: 0.201, 10.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction_2_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction_1_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction_0_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction2_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction2_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction2_3_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction2_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction2_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction2_2_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction3_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction3_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction3_3_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction3_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction3_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction3_2_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/direction3_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/direction3_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/direction3_1_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/sk9822_ck_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/sk9822_ck_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/sk9822_ck_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.285</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.285</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>sk9822_dir/send_bit_cnt_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>6.869</td>
<td>1.869</td>
<td>tNET</td>
<td>FF</td>
<td>sk9822_dir/send_bit_cnt_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sk9822_dir/clk_delay[4]</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sk9822_dir/clk_delay_4_s0/Q</td>
</tr>
<tr>
<td>11.154</td>
<td>1.154</td>
<td>tNET</td>
<td>RR</td>
<td>sk9822_dir/send_bit_cnt_1_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>8274</td>
<td>clk60mhz</td>
<td>-2.503</td>
<td>0.261</td>
</tr>
<tr>
<td>1121</td>
<td>mult_valid</td>
<td>12.674</td>
<td>3.449</td>
</tr>
<tr>
<td>827</td>
<td>clk27mhz_d</td>
<td>-2.585</td>
<td>0.261</td>
</tr>
<tr>
<td>733</td>
<td>n150_5</td>
<td>34.096</td>
<td>1.732</td>
</tr>
<tr>
<td>593</td>
<td>mult_out_valid</td>
<td>13.124</td>
<td>4.114</td>
</tr>
<tr>
<td>577</td>
<td>coeff_ram_addrb[0]</td>
<td>13.752</td>
<td>2.077</td>
</tr>
<tr>
<td>407</td>
<td>led_d_4</td>
<td>13.936</td>
<td>1.944</td>
</tr>
<tr>
<td>321</td>
<td>adder_valid_r0</td>
<td>13.819</td>
<td>3.251</td>
</tr>
<tr>
<td>321</td>
<td>adder_valid_r1</td>
<td>13.800</td>
<td>3.332</td>
</tr>
<tr>
<td>263</td>
<td>delay_shift_addrb_symm[0]</td>
<td>8.666</td>
<td>5.708</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R9C51</td>
<td>91.67%</td>
</tr>
<tr>
<td>R17C52</td>
<td>91.67%</td>
</tr>
<tr>
<td>R21C22</td>
<td>91.67%</td>
</tr>
<tr>
<td>R7C52</td>
<td>90.28%</td>
</tr>
<tr>
<td>R18C43</td>
<td>90.28%</td>
</tr>
<tr>
<td>R36C42</td>
<td>90.28%</td>
</tr>
<tr>
<td>R29C3</td>
<td>90.28%</td>
</tr>
<tr>
<td>R25C17</td>
<td>90.28%</td>
</tr>
<tr>
<td>R25C48</td>
<td>90.28%</td>
</tr>
<tr>
<td>R12C33</td>
<td>90.28%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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